Witam,

Mam problem, pierdylnełem opis na grupę dyskusyjną Xilinxa. Czasami dają sensowne
odpowiedzi, czasami nie. A problem kurde pilny!! Poniżej daję kopię tego co do nich
nabazgrałem po hamerykańsku. Jeżeli macie jakieś pomysły dot. rozwiązania problemu,
to weźcie coś podpowiedzcie. Bo q..va tydzień+ już nad tym ślęczę i nie mam do Pani
Nędzy pomysła jak to rozkminić..

Poniżej szczegóły po hamerykańsku:

Hi,

I've got a problem on my custom board. Based on XC6SLX45-324. OK, let's make you know
what I whant to do. Step by step:

1) Deserialization of data from just only one channel of AD9272. In fact, the logic
works fine according to my idea (2 shift registers+bits aligment). However, it works
fine up to 20MHz main (frame) clock frequency.

2) In fact, I should capture the data from AD9272 reliably @80MHz!!

3) For sure I've got the timing problems, because the design works fine @20MHz and at
higher frequenies fails. NOT a simulation, a real world!! LVDS signals are well
routed on my PCB and equally terminated by both TX/RX devices (AD9272/XCS6SLX45)

3) I've tried to use SelectIO Interface Winard 4.1 . Let's go page by page:

Page 1:

- Component name : del_line (name says what I intend to do. Just a delay of some tap
data delay [ps] in order to match the clocking "eye")

- Data Bus direction: Configure inputs to the device
- I/O signaling : differential
- I/O signaling stardant: LVDS 2.5

Page 2:

All the checkboxes are unchecked, External data width is set to "1".

Page 3:

- Delay Inserted Into Data Routing : I select *FIXED*, initialy set to *0*

Page 4:

- Clock Signaling : Differantial/LVDS 2.5
- Clock Buffer : BUFIO2
- Active Clock Edge : Both Rising and Falling
- Input DDR data aligment : Both Clock Edges: none
- IDDR reset type : ASYNC

Page 5:

Delay inserted Into clock routing : 0

=================

OK, then I click OK, wait a little, report says that the IP has been succesfuly
genrated!!

Well, now I put my new generated module into schematics. New generated module has
such a ports:

Outputs:

DATA_IN_TO_THE_DEVICE(1:0) - no question, understand it as 2 incoming data on pos and
neg clock edge.

Inputs:

DATA_IN_FROM_PINS_P(0:0) - LVDS(+) one wire "bus" as specified on core requirement
DATA_IN_FROM_PINS_N(0:0) - LVDS(-) one wire "bus" as specified on core requirement

CLK_IN_P/N - LVDS input clock pair from external device (AD9512)


======================

ATTENTION!! Here are problematic inputs and outputs:

1) IP core generator makes 2 additional inputs:

- CLK_RESET and IO_RESET. I've GND'ed both of them on my sch. Implementation
process says ERROR about the unknown CLK_RESET pin!

- OK, I've created a new sch module according to IP Core VHDL generated module.
- Implementation : succesfull!!

2) NOTHING on CLK_OUT !! Constant logical '0'.!!

3) For sure, there is no problem on my PCB. When I implement a test design with
CLK+/CLK- into the FPGA => IBUFGDS => CLK any counter => any bit into the output,
then I see on my scope, everything works fine.

4) I'm affraid, that something is wrong with the IP wizard. Can you help me in this
matter?